Ich möchte einen Datensatz initialisieren. Ich habe online und nach dem Stil von this answer aussehen, aber ich erhalte diese Fehler:Warum erhalte ich einen "ungültigen Aggregatfehler" beim Versuch, diesen Datensatz in VHDL zu initialisieren?
Von Aldec Linter:
Compile Architecture "TB_ARCHITECTURE" of Entity "ten_gig_filter_tb" Error: COMP96_0079: mgmt_regs_rx_TB.vhd : (97, 65): Invalid aggregate. Error: COMP96_0077: mgmt_regs_rx_TB.vhd : (97, 65): Undefined type of expression. Expected type 'tAPB_IBUS_RECORD'.
Von XVHDL Linter:
type of aggregate cannot be determined without context; 0 visible types match here, 32 matches.
Hier ist mein Code:
-- APB BUS - CPU interface
type tAPB_IBUS_RECORD is record
pclk : std_logic; --APB Clock, all transactions are synced to this clock
presetn : std_logic; --APB active low reset.
pprot : std_logic_vector(2 downto 0); --APB protection encoding.
pselx : std_logic; --slave select pin, when asserted, will activate the slave
penable : std_logic; -- Enable pin is asserted by the master after the first clock cycle and consecutively until the
-- the end of transcation indicated by pready = '1'
pwrite : std_logic; -- APB Write/Read signal - '1' Write with pselx= '1', '0' - Read along with pselx = '1'
pstrb : std_logic_vector(3 downto 0); -- Write strobe to enable sparse data transfer on the write bus, 0 - byte lane on pwdata(7-0)
paddr : std_logic_vector(19 downto 0); -- 20 bit address bus
pwdata : std_logic_vector(31 downto 0); -- 32 bit data bus
end record;
signal iAPB_BUS_IN : tAPB_IBUS_RECORD := (
pclk => '0', presetn => '0', pprot => (others => '1'),
pselx => '1', pwrite => (others => '0'), penable => '1',
pstrb => (others => '1'), paddr => (others => '0'),
pwdata => (others => '0')
);
Manchmal dauert es nur einen zweiten Satz von Augen. Vielen Dank. – Klik